This application claims priority to Korean Patent Application No. 2004-104633, filed Dec. 11, 2004, the disclosure of which is hereby incorporated herein by reference.
1. Field of the Invention
The present invention relates to integrated circuit devices, and more particularly, to phase locked loop integrated circuits.
2. Description of the Related Art
Phase locked loop (PLL) circuits are widely used in semiconductor integrated circuits, such as application specific integrated circuits, system-on-chips, or memory devices. PLL circuits perform various operations such as frequency synthesis, frequency multiplication, and clock recovery. FIG. 1 is a block diagram of a conventional PLL circuit. This conventional PLL circuit includes a phase frequency detector 11, a charge pump 12, a loop filter 13, a voltage-controlled oscillator 14, and a main divider 15. The phase frequency detector 11 receives an input clock signal IN and compares the phase and frequency of the input clock signal IN with the phase and frequency of a divided clock signal DIN received from the main divider 15. The charge pump 12 receives an output signal of the phase frequency detector 11, and the voltage-controlled oscillator 14 oscillates in response to an output voltage of the charge pump 12. The main divider 15 divides the frequency of a first output clock signal OUT of the voltage-controlled oscillator 14 and outputs the divided clock signal DIN. These and other aspects of the PLL of FIG. 1 are more fully illustrated and described in section 9.5.2 of a textbook by Jan M. Rabaey, entitled Digital Integrated Circuits: A Design Perspective, Prentice-Hall, ISBN 0-13-178609-1, pp. 540-542.
Ideally, a conventional PLL circuit may continuously perform a looping operation until the PLL is locked to a desired frequency. However, if the frequency of the first output clock signal OUT of the voltage-controlled oscillator 14 is above a threshold frequency, the main divider 14 may not be able to perform its operation sufficiently, and thus, a deadlock condition, which is a phenomenon related to poor locking of the conventional PLL circuit, may occur.